1. Field
Embodiments of the present invention relate to a method of manufacturing a reverse blocking insulated gate bipolar transistor (hereinafter simply referred to as IGBT), and in particular to a method that provides an IGBT with the reliability of reverse blocking ability equivalent to the reliability of forward blocking ability, whereas only the latter reliability is generally secured in traditional IGBTs.
2. Description of the Related Art
A reverse blocking IGBT needs reverse blocking ability as reliable as the forward blocking ability of traditional IGBTs. In order to achieve high reliability of the reverse blocking ability, it is necessary to bend a reverse blocking pn junction in the back surface side, which is normally formed flat, around the side wall of the semiconductor chip substrate and extend the end portion of the pn junction from the back surface side to the front surface side of the chip substrate. The term ‘isolation layer’ in this specification means a diffusion layer forming the bent pn junction extending from the back surfaced side to the front surface side.
FIGS. 6A, 6B, and 6C are sectional views of the essential part of a semiconductor substrate showing solely a process of forming an isolation layer of a conventional reverse blocking IGBT. Fundamentally, this process for forming an isolation layer is a process of application and diffusion. A thick semiconductor substrate 1 with a diameter of six inches and a thickness of 625 μm is prepared. An oxide film 2 about 2.5 μm thick is formed on the substrate 1 for use as a dopant mask by thermal oxidation as shown in FIG. 6A. Then, an opening 3 is formed by patterning etching on the oxide film 2, for forming an isolation layer 4, as shown in FIG. 6B.
Then, boron source 5 is applied on the opening 3 and heat treatment is conducted in a diffusion furnace at a high temperature for a long time to form a p type isolation layer 4 with a depth of several hundred microns as shown in FIG. 6C. A reverse blocking IGBT for a breakdown voltage of 1,200 V class, for example, requires isolation layer 4 to have a depth of 200 μm. Forming an isolation layer 200 μm deep needs heat treatment at a high temperature of 1,300° C. for about 300 hr. A reverse blocking IGBT of 1,700 V class needs thermal diffusion process at the high temperature of 1,300° C. and a long thermal diffusion time of 600 hr. In order to utilize the isolation function of the isolation layer 4 at this stage, the wafer must be made thin by grinding from the back surface in a later step down to the position of the dotted line in FIG. 6C.
FIGS. 4A to 4E are sectional views of a semiconductor substrate showing a conventional method of manufacturing a reverse blocking IGBT. FIG. 4A is a sectional view of the semiconductor substrate at the stage of completion of the process for forming the isolation layer 4 described above. The region between the dotted lines 8 in FIG. 4E through the center of the isolation layer 4, formed from the front surface of the substrate, corresponds to one chip of a reverse blocking IGBT. A reverse blocking IGBT needs a MOS gate structure 10 formed on the front surface of the substrate as shown in FIG. 4B, which does not depict a detailed MOS gate structure because it is too precise to be illustrated in the figure. After that, the semiconductor substrate 1 is made thin by grinding from the back surface until the bottom of the isolation layer 4 is exposed as shown in FIG. 4C. FIGS. 4D and 4E show a back surface structure composed of a p collector layer 6 and a collector electrode 7 formed on this exposed isolation layer. The semiconductor substrate 1 is cut along the scribing lines 8 at the center of the isolation layer 4 shown in FIG. 4E to obtain reverse blocking IGBTs. FIG. 7 shows the cross section including the end region of the finished reverse blocking IGBT.
FIGS. 8A, 8B, and 8C are sectional views of an essential part of a reverse blocking IGBT showing a process for forming an isolation layer 4 in the sequence of process steps; the process is a conventional one but different from the one shown in FIGS. 6A, 6B, and 6C. In brief, this process forms an isolation layer 4 by digging a trench 11 vertically from the front surface of the semiconductor substrate 1 and forms a diffusion layer on the side wall surface of the trench. Specifically, a relatively thick oxide film 2 with a thickness of several microns is first formed on the substrate 1, as shown in FIG. 8A. After forming an opening through the oxide film 2, a trench 11 is formed to a depth of several hundred microns by anisotropic dry etching as shown in FIG. 8B. Then, the isolation layer 4, a diffusion layer, is formed by introducing impurities on the side wall surface of the trench 11 by means of a vapor phase diffusion process as shown in FIG. 8C. In FIG. 9, a MOS gate structure 10 is formed on the front surface and the trench 11 is filled with a reinforcing material such as polysilicon or an insulation film. After that, the semiconductor substrate is made thin by grinding from the back surface to a position close to the isolation layer 4. A back surface structure like the one shown in FIG. 4E is formed. The semiconductor substrate 1 is cut with a dicing process along scribe lines 8 into IGBT chips. Thus, a reverse blocking IGBT is obtained; FIG. 9 is an enlarged sectional view of the obtained IGBT showing the end region thereof.
Techniques to form an isolation layer on the side wall surface of a trench are disclosed in Patent Documents 1 through 3. In the manufacturing method disclosed in Patent Document 1, a deep vertical trench is formed surrounding the active device region of a semiconductor element from the upper surface of the device chip to a depth reaching a pn junction in the lower surface region. On the side wall surface of the trench, a p type diffusion layer, an isolation layer, is formed and connected to a p type diffusion layer in the lower surface region. Thus, the pn junction in the lower surface region of the device is bent and extended to the upper surface region with the isolation layer. Patent Documents 2 and 3, like Patent Document 1, also disclose a device exhibiting reverse blocking ability that has a trench formed from the upper surface of the device to reach a pn junction in the lower surface region and a diffusion layer is formed on the side wall surface of the trench.
The method shown in FIGS. 6A, 6B, and 6C depicts the formation of an isolation layer of a reverse blocking IGBT by means of an application and diffusion process. A boron source, which is a diffusion source of boron in a liquid state, is applied on the front surface and diffused by heating. In order to obtain an isolation layer with a diffusion depth of several hundred microns, the diffusion process must be conducted at a high temperature for a long time. In addition to the issues mentioned earlier, this causes inevitable problems of distortion of quartz jigs that lead to the construction of a diffusion furnace including a quartz boat, a quartz tube, and a quartz nozzle; contamination due to a heater; and decreased strength due to devitrification of the quartz jigs.
The application and diffusion process for forming an isolation layer must form a mask of oxide film. This mask of oxide film must be a thick and good quality oxide film to endure the boron diffusion process for a long time. Thermally oxidized films are used to obtain a mask of high durability, or a silicon oxide film of good quality. The thermal oxidation film must have a thickness of at least 2.5 μm to prevent boron atoms from penetrating through the mask oxide film during the diffusion process of boron used to form the isolation layer at a high temperature for a long time, for example, 1,300° C. for 200 hr. Forming a thermal oxidation film with a thickness of 2.5 μm requires an oxidation time of about 200 hr at an oxidation temperature of 1,150° C., for example, and in a dry oxygen atmosphere, which provides an oxide film of good quality.
A wet oxidation process or pyrogenic oxidation process may be employed to perform the oxidation in a shorter time than the dry oxidation process, although film quality is inferior to that of the dry process. The wet and pyrogenic processes still require an oxidation time of about 15 hr, which is not a satisfactorily short time. Moreover, these oxidation processes introduce a large amount of oxygen atoms into the silicon semiconductor substrate forming oxygen precipitation and lattice defects such as oxidation-induced stacking faults (OSFs) to create oxygen donors that deteriorate performance and degrade reliability of the device.
The thermal diffusion, after boron source application, is carried out at a high temperature for a long time usually in an oxygen atmosphere. This also introduces interstitial oxygen atoms into the semiconductor substrate causing oxygen precipitation, donor-creating phenomenon, and generation of lattice defects such as the OSFs and slip dislocations. These lattice defects are known to increase the leakage current at the pn junction in the semiconductor substrate and deteriorate breakdown voltage and reliability of insulation films created in the diffusion process on the semiconductor substrate. The oxygen donors lower the breakdown voltage.
Further, in the method of forming an isolation layer shown in FIGS. 6A, 6B, and 6C, the thermal diffusion of boron proceeds from the opening in the mask oxide film into the body of the silicon substrate in an isotropic way. Therefore, boron diffusion of 200 μm in the depth direction accompanies lateral diffusion of about 160 μm. This increases a device pitch and a chip size, which raises a chip cost.
In the method to form an isolation layer shown in FIGS. 8A, 8B, and 8C, a trench is formed by means of a dry etching process, and an isolation layer is formed by introducing boron into the side wall of the trench. The trench is then filled with a reinforcing material, such as an insulation film, and formed with a high aspect ratio. The method depicted in FIGS. 8A, 8B, and 8C is advantageous compared with the method depicted in FIGS. 6A, 6B, and 6C in terms of device pitch reduction because of smaller lateral expansion of the isolation layer in the method of FIGS. 8A, 8B, and 8C.
However, the etching process to a depth of about 200 μm requires a processing time of about 100 min for one sheet, using a typical dry etching apparatus, and thus results in inevitable drawbacks of prolonged lead time and increased maintenance frequency. When a deep trench is formed by a dry etching process using a mask of a silicon oxide film, a selection ratio is smaller than 50, which requires a silicon oxide film of several microns thick. This raises costs and lowers the rate of non-defective products caused by creation of process-induced lattice defects such as oxidation-induced stacking faults and oxygen precipitation.
In addition, the process of forming an isolation layer using a trench with a high aspect ratio, deeply dug by dry etching has technological problems that have not been completely eliminated. These problems concern the removal of residual chemical liquid and resist residues in the trench. Thus, this results in lowered yield and deteriorated reliability. Introduction of a dopant, such as phosphorus or boron into the side wall of a trench, is carried out by an ion injection process. This is usually done with the semiconductor substrate tilted because of vertical configuration of the trench side wall. However, the dopant introduction into the side wall of a trench with a high aspect ratio has drawbacks, including lowered effective dose, elongated injection time, decreased effective projection range, loss of dose due to screening oxidation film, and deteriorated injection uniformity. As an alternative to the ion injection, a vapor phase diffusion process may be employed for introducing impurities into a trench with a high aspect ratio. In the vapor phase diffusion process, the semiconductor substrate is exposed to a dopant atmosphere of vaporized phosphine PH3, diborane B2H6, or the like. However, this process is inferior to the ion injection process in terms of precise control of dose amount.
The insulation film, filled into a trench with a high aspect ratio, can contain voids that cause problems of reliability. The manufacturing methods disclosed in Patent Documents 1, 2, and 3 require filling the trench with a reinforcing material to prevent the wafer from cracking before cutting the semiconductor substrate into semiconductor chips at scribe lines. This additional filling with a reinforcing material raises production costs.
Some means for solving the problems described thus far have been disclosed. For example, a tapered groove, in place of the perpendicular trench, can be formed with the side wall of the groove and tilted to a certain angle with respect to the principal surface of a substrate so that the surface area of an emitter side (or a collector side) is smaller than that of a collector side (or an emitter side). Chips with the tilted side wall of the tapered groove allow ion injection into the tilted side wall and annealing in the state of a wafer. Therefore, the problems mentioned above can be eliminated and isolation layers can be formed more easily.
In the method disclosed in Patent Documents 4 and 5, a tapered groove is formed by a selective anisotropic etching process in such a configuration that the side wall of the tapered groove is tilted so that the surface area in the emitter side is smaller than that in the collector side. In contrast, Patent Document 6 discloses a reverse blocking IGBT with a tapered side wall surface where the surface area is larger in the emitter side than in the collector side. The reverse blocking IGBT of Patent Document 6 utilizes a broader emitter side wall surface than the devices of Patent Documents 4 and 5. A broader area can be used for an n emitter region and a p base region that are formed in the surface region of the emitter side. Consequently, the current density is higher and the chip area is smaller for a given current rating. In the reverse blocking IGBT with a tapered groove, the isolation layer is formed by the processes of ion injection and annealing. This solves the above problems of lattice defects and oxygen-induced defects and damages on the furnace associated with the thermal diffusion for a long time. The aspect ratio is lower as compared with the manufacturing method to deeply dig a trench as shown in FIGS. 8A, 8B, and 8C. The process of forming the tapered groove does not have the problem of chemical liquid residue or resist residue. Introduction of dopant can be readily carried out into the tilted side wall surface by ion injection.
Patent Document 7 discloses a technique to enhance an activation rate by ion injection with the semiconductor substrate heated at temperatures in the range of 400° C. to 500° C.    [Patent Document 1]            Japanese Unexamined Patent Application Publication No. H02-022869            [Patent Document 2]            Japanese Unexamined Patent Application Publication No. 2001-185727            [Patent Document 3]            Japanese Unexamined Patent Application Publication No. 2002-076017            [Patent Document 4]            Japanese Unexamined Patent Application Publication No. 2006-156926            [Patent Document 5]            Japanese Unexamined Patent Application Publication No. 2004-336008            [Patent Document 6]            Japanese Unexamined Patent Application Publication No. 2006-303410            [Patent Document 7]            Japanese Unexamined Patent Application Publication No. 2005-268487        
A reverse blocking IGBT with a tapered groove, disclosed in Patent Documents 4, 5, and 6, has a thin (or shallow) isolation layer because it is formed by a method that does not use long time diffusion. As a consequence, lattice defects accompanying the ion injection process remain in the vicinity of a pn junction if the lattice defects are not fully cured by an annealing process. Thus, leakage current in reverse-biased condition is likely to become large, resulting in a lower reverse blocking voltage than the predetermined design value.
In the known annealing processes of laser annealing and activation annealing using a flash lamp, activation of the isolation layer may be insufficient. Lattice defects remain if accurate control is not performed on focusing position, which is the location necessary for proper activation of the isolation layer on the tapered groove during the lamp annealing process.